9. MemTypes Package

9.1. Constants

typedef MemTypes::Bit#(32) SGLId

typedef MemTypes::44 MemOffsetSize

typedef MemTypes::6 MemTagSize

typedef MemTypes::8 BurstLenSize

typedef MemTypes::32 MemServerTags

typedef MemTypes::TDiv#(DataBusSize,8) ByteEnableSize

9.2. Data Types

struct MemTypes::PhysMemRequest#(numeric type addrWidth, dataWidth)

A memory request containing a physical memory address

addr → Bit#(addrWidth)

Physical address to read or write

burstLen → Bit#(BurstLenSize)

Length of read or write burst, in bytes. The number of beats of the request will be the burst length divided by the physical width of the memory interface.

tag → Bit#(MemTagSize)

firstbe → Bit#(TDiv#(dataWidth,8))

lastbe → Bit#(TDiv#(dataWidth,8))

If BYTE_ENABLESis defined as aBSV preprocessor macro,byte write enables are added to PhysMemRequest, intwo fields: firstbe and lastbe.The idea is to enable writing any number of contiguous bytes even if it is less than the width of the shared memory data bus.

These have roughly the same semantics as in PCIE. The write enable in firstbe apply to the first beat of a burst request and those inlastbe apply to the last beat of a multi-beat burst request. Intervening beats of a burst request enable the write of all beats of that burst.

struct MemTypes::MemRequest

A logical memory read or write request. The linear offset of the request will be translated by an MMU according to the specified scatter-gather list.

sglId → SGLId

Indicates which scatter-gather list the MMU should use when translating the address

offset → Bit#(MemOffsetSize)

Linear byte offset to read or write.

burstLen → Bit#(BurstLenSize)

Length of read or write burst, in bytes. The number of beats of the request will be the burst length divided by the physical width of the memory interface.

tag → Bit#(MemTagSize)

firstbe → Bit#(ByteEnableSize)

lastbe → Bit#(ByteEnableSize)

If BYTE_ENABLESis defined as aBSV preprocessor macro,byte write enables are added to PhysMemRequest, intwo fields: firstbe and lastbe.The idea is to enable writing any number of contiguous bytes even if it is less than the width of the shared memory data bus.

These have roughly the same semantics as in PCIE. The write enable in firstbe apply to the first beat of a burst request and those inlastbe apply to the last beat of a multi-beat burst request. Intervening beats of a burst request enable the write of all beats of that burst.

struct MemTypes::MemData#(numeric type dsz)

One beat of the payload of a physical or logical memory read or write request.

data → Bit#(dsz)

One data beat worth of data.

tag → Bit#(MemTagSize)

Indicates to which request this beat belongs.

last → Bool

Indicates that this is the last beat of a burst.

struct MemTypes::MemDataF#(numeric type dsz)

One beat of the payload of a physical or logical memory read or write request. Used by MemReadEngine and MemWriteEngine.

data → Bit#(dsz)

One data beat worth of data.

tag → Bit#(MemTagSize)

Indicates to which request this beat belongs.

first → Bool

Indicates that this is the first data beat of a request.

last → Bool

Indicates that this is the last data beat of a request.

9.3. Physical Memory Clients and Servers

interface MemTypes::PhysMemMaster(numeric type addrWidth, numeric type dataWidth)

The physical memory interface exposed by MemMaster. For example, connects via AXI to Zynq or via PCIe to x86 memory.

read_client → PhysMemReadClient#(addrWidth, dataWidth)

write_client → PhysMemWriteClient#(addrWidth, dataWidth)

interface MemTypes::PhysMemReadClient(numeric type asz, numeric type dsz)

readReq → Get#(PhysMemRequest#(asz))

readData → Put#(MemData#(dsz))

interface MemTypes::PhysMemWriteClient(numeric type asz, numeric type dsz)

writeReq → Get#(PhysMemRequest#(asz))

writeData → Get#(MemData#(dsz))

writeDone → Put#(Bit#(MemTagSize))

interface MemTypes::PhysMemSlave(numeric type addrWidth, numeric type dataWidth)

read_server → PhysMemReadServer#(addrWidth, dataWidth)

write_server → PhysMemWriteServer#(addrWidth, dataWidth)

interface MemTypes::PhysMemReadServer(numeric type asz, numeric type dsz)

readReq → Put#(PhysMemRequest#(asz))

readData → Get#(MemData#(dsz))

interface MemTypes::PhysMemWriteServer(numeric type asz, numeric type dsz)

writeReq → Put#(PhysMemRequest#(asz))

writeData → Put#(MemData#(dsz))

writeDone → Get#(Bit#(MemTagSize))

9.4. Memory Clients and Servers

These clients and servers operate on logical addresses. These are translated by an MMU before being issued to system memory.

interface MemTypes::MemReadClient(numeric type dsz)

The system memory read interface exported by a client of MemServer, such as MemReadEngine.

readReq → Get#(MemRequest)

readData → Put#(MemData#(dsz))

interface MemTypes::MemWriteClient(numeric type dsz)

The system memory write interface exported by a client of MemServer, such as MemWriteEngine.

writeReq → Get#(MemRequest)

writeData → Get#(MemData#(dsz))

writeDone → Put#(Bit#(MemTagSize))

interface MemTypes::MemReadServer(numeric type dsz)

The system memory read interface exported by MemServer.

readReq → Put#(MemRequest)

readData → Get#(MemData#(dsz))

interface MemTypes::MemWriteServer(numeric type dsz)

The system memory write interface exported by MemServer.

writeReq → Put#(MemRequest)

writeData → Put#(MemData#(dsz))

writeDone → Get#(Bit#(MemTagSize))

9.5. Memory Engine Types

struct MemTypes::MemengineCmd

A read or write request for a MemReadEngine or a MemWriteEngine. MemRead and MemWrite engines will issue one or more burst requests to satisfy the overall length of the request.

sglId → SGLId

Which memory object identifer (scatter gather list ID) the MMU should use to translate the addresses

base → Bit#(MemOffsetSize)

Logical base address of the request, as a byte offset

burstLen → Bit#(BurstLenSize)

Maximum burst length, in bytes.

len → Bit#(32)

Number of bytes to transfer. Must be a multiple of the data bus width.

tag → Bit#(MemTagSize)

Identifier for this request.

9.6. Memory Engine Interfaces

interface MemTypes::MemWriteEngineServer(numeric type userWidth)

The interface used by one client of a MemWriteEngine.

request → Put#(MemengineCmd)

done → Get#(Bool)

data → PipeIn#(Bit#(userWidth))

interface MemTypes::MemWriteEngine(numeric type busWidth, numeric type userWidth, numeric type cmdQDepth, numeric type numServers)

A multi-client component that supports multi-burst writes to system memory.

dmaClient → MemWriteClient#(busWidth)

writeServers → Vector#(numServers, MemWriteEngineServer#(userWidth))

interface MemTypes::MemReadEngineServer(numeric type userWidth)

The interface used by one client of a MemReadEngine.

request → Put#(MemengineCmd)

data → PipeOut#(MemDataF#(userWidth))

interface MemTypes::MemReadEngine(numeric type busWidth, numeric type userWidth, numeric type cmdQDepth, numeric type numServers)

A multi-client component that supports multi-burst reads from system memory.

dmaClient → MemReadClient#(busWidth)

readServers → Vector#(numServers, MemReadEngineServer#(userWidth))

9.7. Memory Traffic Interfaces

interface MemTypes::DmaDbg

getMemoryTraffic → ActionValue#(Bit#(64))

dbg → ActionValue#(DmaDbgRec)

9.8. Connectable Instances

instance MemTypes::Connectable(MemReadClient#(dsz), MemReadServer#(dsz))

instance MemTypes::Connectable(MemWriteClient#(dsz), MemWriteServer#(dsz))

instance MemTypes::Connectable(PhysMemMaster#(addrWidth, busWidth), PhysMemSlave#(addrWidth, busWidth))

instance MemTypes::Connectable(PhysMemMaster#(32, busWidth), PhysMemSlave#(40, busWidth))