1. Invocation of makefilegen.py¶

The makefilegen.py script generates project Makefiles. Normally, it is invoked from Makefile.connectal and passed options via CONNECTALFLAGS.

1.1. Project Options¶

-B board, --board=board¶: Specifies which board to build for.

--O os, --option=os¶: Specifies which operating system to support. Usually derived from :option:board.

--project-dir=dir¶: Specifies the directory in which to creat the Makefile that performs the build. Creates the directory if it does not exist.

1.2. Source Options¶

bsvfile¶: This positional argument specifies which BSV files to parse for type and interface declarations.

-s foo.cpp, --source=foo.cpp¶: Specifies C and C++ files to include in the application.

--ipdir=dir¶: Specifies where to store IP cores generated by Vivado or Quartus

--cachedir=dirname¶: Specifies directory to be used by buildcache

--nocache¶: Disables buildcache

-D var=value¶: Binds var to value in software, BSV, Verilog, and Tcl contexts.

-v, --verbose¶: Verbose operation

1.3. Interface Options¶

--interfaces=...¶: To be written…

--dump_map¶: Generate a JSON file describing the portals, for use in tracing tools such as pcieflat.

1.4. Software Options¶

--cflags=flags¶: Specifies build flags for the C/C++ compiler

-I dir --cinclude=dir¶

-l lib, --clib=lib¶: Link the application with library lib.

-S libfile, --clibfiles=libfile.a¶: Link the application with library file libfile.a.

-L libdir, --clibdir=libdir¶: Addes libdir to the software library path.

--nonstrict¶: Pass –Wall to gcc instead of -Werror.

--shared¶: Specifies to build a shared library instead of an executable.

--nohardware¶: Suppresses build of hardware, for software-only projects.

--stl=stltype¶

Specifies which C++ Standard Template Library to use for Android. The choices are:

stlport_static: STLport runtime C++ exceptions and RTTI and Standard Template Library

stlport_shared

gnustl_static: GNU STL runtime C++ exceptions and RTTI and Standard Template Library

gnustl_shared

c++_static: LLVM libc++ runtime C++ exceptions and RTTI and Standard Template Library

c++_shared

gabi++_static: GAbi++ runtime C++ exceptions and RTTI

gabi++_shared

1.5. Hardware Options¶

--bsvpath=dirname¶: Adds dirname to the BSV module import path.

-b options, --bscflags=options¶: Flags to pass to the BSV compiler.

-V file.v, --verilog=file.v¶: Specifies verilog file to include in the design

--pinfo=project.json¶: This does what?

--pinout=pinusage.json¶

Specifies connection of pins on the board to top level signals of the design. A board-specific constraint file will be generated from pinusage.json and the boardinfo json file, and will be added to constraint and implconstraint.

See :make:var::PINOUT_FILE, whose values are passed as –pinout options to makefilegen.

--constraint=file.xdc¶: Specifies synthesis phase constraint file.

--implconstraint=file.xdc¶: Specifies implementation (place and route) constraint file.

--unmanaged-implconstraint=file.xdc¶: Specifies unmanaged implementation (place and route) constraint file. This causes the xdc file to be read in using the -unmanaged flag of read_xdc. This allows the xdc files to use more tcl commands than a normal xdc file (including if and foreach).

-P modulename, --partition=modulename¶: Directs fpgamake to build a separate netlist for modulename. With buildcache, Reduces build times if module changes infrequently.

1.6. Xilinx Options¶

--xci=core.xci¶: Specifies IP core to include in the design. (Xilinx only)

1.7. Altera Options¶

--qip=core.qip¶: Specifies IP core to include in the design. (Altera only)

--qsf=settings.qsf¶: Specifies Altera Quartus settings.

1.8. Partial Reconfiguration Options¶

--prtop=mkTop.dcp¶: Specifies filename of previously built top level.

--prvariant=name¶: …

--reconfig=modulenames¶: …

1.9. Bluesim Options¶

-q, --qtused¶: Link the bluesim bsim executable with libQt.

-m foo.cpp, --bsimsource foo.cpp¶

Specifies additional sources to compile into the bsim executable. If you are using Bluespec import “BDPI” or SystemVerilog “DPI”/”DPI-C”, you will need to link additional sources into the simulator.

Note: These files are currently compiled with g++, even if they are C files. You will need to use extern “C” to export symbols to the simulator.

1.10. Xsim Options¶

--xelabflags=flags¶: Options to pass to xelab

--xsimflags¶: Options to pass to xsim

1.11. Clocking Options¶

--mainclockperiod¶

Specifies the period, in nanoseconds, of the main clock. Must be an integer.

On Zynq boards,

On PCIe-connected boards, if the main clock period differs from the PCIe clock period, then the design’s portals and DMA ports will automatically be connected via SyncFIFO’s.

Each boardinfo JSON file specifies the default value for mainclockperiod.

--derivedclockperiod¶

Connectal also makes a second clock available, host.derivedClock. The period of this clock is